transcript on
if {[file exists gate_work]} {
	vdel -lib gate_work -all
}
vlib gate_work
vmap work gate_work

vcom -93 -work work {test1_6_1200mv_85c_slow.vho}

vcom -93 -work work {C:/Users/Jerrymin/Desktop/Projs/FPGA_Projs/1_1_3/simulation/modelsim/test1.vht}

vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /NA=test1_6_1200mv_85c_vhd_slow.sdo -L altera_mf -L altera -L lpm -L sgate -L cycloneiv_hssi -L cycloneiv_pcie_hip -L cycloneiv -L gate_work -L work -voptargs="+acc"  test1_vhd_tst

add wave *
view structure
view signals
run 2 sec
